TDA3MV Datasheet, PDF (15/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
BALL NUMBER [1]
BALL NAME [2]
Y17
AB18
AA3
AA2
Y3
V2
U3
V3
Y2
Y1
U21
T20
R21
U20
R22
V20
W22
U22
AB8
Y18
AB3
W21
AA5
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
Table 4-2. Ball Characteristics⁽¹⁾ (continued)
SIGNAL NAME [3]
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
MA/LX/LA MUXMODE
[4]
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
I/O
REL. VOLTAGE
MUXMODE VALUE [10]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
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Terminal Configuration and Functions
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