TDA3MV Datasheet, PDF (132/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
GPMC_FCLK
gpmc_clk
gpmc_csi
gpmc_a[27:1]
gpmc_ben0
gpmc_ben1
gpmc_advn_ale
gpmc_oen_ren
gpmc_ad[15:0]
gpmc_waitj
FA21
FA9
FA10
Add0
FA10
FA12
FA13
FA20
FA1
FA20 FA20
Add1 Add2 Add3
FA0
FA0
Add4
FA18
D0
D1
D2
D3
D3
FA15
FA14
DIR
OUT
IN
OUT
SPRS91v_GPMC_09
Figure 7-12. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing^(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note (ref …) and should be stored inside
AccessTime register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
132 Timing Requirements and Switching Characteristics
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