TDA3MV Datasheet, PDF (192/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 and LP8732 combined with LP8733 PMICs.
TPS65917
SMPS1
SMPS2
SMPS3
SMPS4
Table 8-4. Power Supply Connections
Dual Converter Solution
LP8733Q Buck0
LP8733Q Buck1
LP8732Q Buck0
LP8732Q Buck1
Valid Combination 1:
vdd_dspeve
vdd
vdds18v, vdds18v_ddr[3:1], vddshv[6:1]
vdds_ddr1, vdds_ddr2, vdds_ddr3
Table 8-5 illustrates the LP8733 and LP8732 OTP IDs required for TDA3 processor systems using
different DDR memory types.
DDR Type
DDR2
LPDDR2
DDR3
DDR3L
Table 8-5. OTP ID Memory Types Support
LP8733Q
OTP Version
2A
2A
2A
2A
LP8732Q
OTP Version
2D
2B
2F
2E
8.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 PMIC LDOLN output or LDO0 on LP8733Q dual power solution is specifically designed to
meet this low noise requirement.
NOTE
For more information about Input Voltage Sources, see DPLLs, DLLs Specifications
Table 8-6 presents the voltage inputs that supply the DPLLs.
Table 8-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
vdda_ddr_dsp
vdda_gmac_core
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_DSP, DPLL_DDR and DDR HSDIVIDER analog power supply
GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER analog power
supply
192 Applications, Implementation, and Layout
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA