TDA3MV Datasheet, PDF (159/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 7-29. Switching Characteristics Over Recommended Operating Conditions for McASP1
(1) _(continued)
NO. PARAMETER DESCRIPTION
14
t _d(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
MODE
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
MIN MAX UNIT
0
6
ns
2
22.2
ns
Table 7-30. Switching Characteristics Over Recommended Operating Conditions for McASP2 ⁽¹⁾
NO. PARAMETER DESCRIPTION
9
t_c(AHCLKX)
10
t_w(AHCLKX)
Cycle time, AHCLKX
Pulse duration, AHCLKX high or low
11
t_c(ACLKRX)
12
t_w(ACLKRX)
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
13 t _{d(ACLK-AFSXR)} Delay time, ACLKR/X transmit edge to AFSX/R output
valid
14
t _d(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
MODE
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
MIN
20
0.5P -
2.5 ⁽²⁾
20
0.5P -
2.5 ⁽³⁾
0
2
MAX
6
22.2
UNIT
ns
ns
ns
ns
ns
ns
0
6
ns
2
22.2
ns
Table 7-31. Switching Characteristics Over Recommended Operating Conditions for McASP3 ⁽¹⁾
NO. PARAMETER DESCRIPTION
9
t_c(AHCLKX)
10
t_w(AHCLKX)
Cycle time, AHCLKX
Pulse duration, AHCLKX high or low
11
t_c(ACLKRX)
12
t_w(ACLKRX)
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
13 t _{d(ACLK-AFSXR)} Delay time, ACLKR/X transmit edge to AFSX/R output
valid
14
t _d(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output
valid
MODE
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
MIN
20
0.5P -
2.5
20
0.5P -
2.5
0
2
MAX
6
23.1
UNIT
ns
ns
ns
ns
ns
ns
0
6
ns
2
23.1
ns
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Timing Requirements and Switching Characteristics 159
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