English
Language : 

TDA3MV Datasheet, PDF (92/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
IOLmin Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)
6
tOF
Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF
to 400 pF
I2C Fast Mode – 3.3 V
mA
250
ns
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys Hysteresis
0.7*VDDS
0.05*VDD
S
V
0.3*VDDS
V
V
II
Input current at each I/O pin with an input voltage between 0.1*VDDS to
31
0.9*VDDS
80
µA
IOZ
CI
VOL3
IOLmin
IOLmin
tOF
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
Input capacitance
Output low-level threshold open-drain at 3-mA sink current
Low-level output current @VOL=0.4V
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10
pF to 200 pF (Proper External Resistor Value should be used as per I2C
spec)
31
3
6
20+0.1*Cb
80
µA
10
pF
0.4
V
mA
mA
250
ns
Output fall time from VIHmin to VILmax with a bus capacitance CB from 300
40
290
pF to 400 pF (Proper External Resistor Value should be used as per I2C
spec)
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see POWER column.
5.7.3 IQ1833 Buffers DC Electrical Characteristics
Table 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
Table 5-12. IQ1833 Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: tclk;
Balls ABF: J2;
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
MIN
NOM
0.75 *
VDDS
VHYS
Input hysteresis voltage
100
IIN
Input current at each I/O pin
2
CPAD
Pad capacitance (including package capacitance)
3.3-V Mode
VIH
VIL
VHYS
IIN
CPAD
Input high-level threshold
2.0
Input low-level threshold
Input hysteresis voltage
400
Input current at each I/O pin
5
Pad capacitance (including package capacitance)
MAX
0.25 *
VDDS
11
1
0.6
11
1
UNIT
V
V
mV
µA
pF
V
V
mV
µA
pF
92
Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA