TDA3MV Datasheet, PDF (245/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
DQLMY2
DQLMX0
DB0
DQ[0:7]/DM0/DQS0
DB1 ^{DQ[8:15]/DM1/DQS1}
DQLMX1
DB2 ^{DQ[16:23]/DM2/DQS2}
DQLMX2
DQLMY1
DQLMY0
2
1
0
DB0 - DB2 represent data bytes 0 - 2.
SPRS91v_PCB_DDR3_28
There are three DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
Figure 8-71. DQLM for Any Number of Allowed DDR3 Devices
Table 8-45. Data Routing Specification⁽²⁾
NO.
PARAMETER
MIN
TYP
MAX
UNIT
DRS31 DB0 length
340
ps
DRS32 DB1 length
340
ps
DRS33
DRS35
DB2 length
DBn skew⁽³⁾
340
ps
5
ps
DRS36
DRS37
DQSn+ to DQSn- skew
DQSn to DBn skew⁽³⁾⁽⁴⁾
DRS38 Vias per trace
DRS39 Via count difference
DRS310 Center-to-center DBn to other DDR3 trace spacing⁽⁶⁾
4
DRS311 Center-to-center DBn to other DBn trace spacing⁽⁷⁾
3
DRS312 DQSn center-to-center spacing⁽⁸⁾⁽⁹⁾
DRS313 DQSn center-to-center spacing to other net
4
1
5⁽¹⁰⁾
2⁽¹⁾
0⁽¹⁰⁾
ps
ps
vias
vias
w⁽⁵⁾
w⁽⁵⁾
w⁽⁵⁾
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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Applications, Implementation, and Layout 245
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