TDA3MV Datasheet, PDF (107/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 6-8. OSC1 Input Clock Timing Requirements
NAME
CK0
CK1
1 / t_c(xiosc1)
t_w(xiosc1)
t_j(xiosc1)
t_R(xiosc1)
t_F(xiosc1)
t_j(xiosc1)
DESCRIPTION
Frequency, xi_osc1
Pulse duration, xi_osc1 low or high
Period jitter⁽¹⁾, xi_osc1
Rise time, xi_osc1
Fall time, xi_osc1
Frequency accuracy⁽²⁾, xi_osc1
Ethernet not used
Ethernet RGMII using
derived clock
MIN
TYP
MAX
Range from 12 to 38.4
0.45 × t_c(xiosc1)
0.55 × t_c(xiosc1)
0.01 × t_c(xiosc1)(3)
5
5
±200
±50
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*t_c(xiosc1) under the following constraints:
a. The osc1/SYS_CLK2 clock bypasses all device PLLs
b. The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
UNIT
MHz
ns
ns
ns
ns
ppm
ppm
CK0
xi_osc1
CK1
CK1
Figure 6-9. xi_osc1 Input Clock
SPRS91v_CLK_07
6.1.4 RC On-die Oscillator Clock
RCOSC_32K_CLK is received directly through a network of resistor and capacitor (an RC network) inside
of the SoC. This RC oscillator do not have good frequency stability. The Frequency range is described in
Table 6-9, which depends on the temperature. For more information about RCOSC_32K_CLK see the
Device TRM, Chapter: Power, Reset, and Clock Management.
Table 6-9. RC On-die Oscillator Clock Frequency Range
NAME
DESCRIPTION
RCOSC_32K_CLK Internal RC Oscillator
MIN
TYP
MAX
Range from 28 to 42
UNIT
kHz
6.2 DPLLs, DLLs Specifications
For more information, see:
NOTE
• Power, Reset, and Clock Management / Clock Management Functional Description /
Internal Clock Sources / Generators / Generic DPLL Overview Section
and
• Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module.
• They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
• They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
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Clock Specifications 107