TDA3MV Datasheet, PDF (82/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name Clock Type
EMIF_PHY
EMIF
ESM
EVE
EMIF_PHY1_FCLK
EMIF1_ICLK
EMIF_L3_ICLK
EMIF_PHY_FCLK
EMIF_DLL_FCLK
OCP_CLK
EVE_FCLK
Func
Int
Int
Func
Int
Int
Func
GMAC_SW
CPTS_RFT_CLK
Func
MAIN_CLK
MHZ_250_CLK
MHZ_5_CLK
MHZ_50_CLK
GPIO1
GPIO1_ICLK
GPIO1_DBCLK
GPIO2
GPIO3
GPIO4
GPMC
GPIO2_ICLK
GPIO2_DBCLK
GPIO3_ICLK
GPIO3_DBCLK
GPIO4_ICLK
GPIO4_DBCLK
GPMC_ICLK
I2C1
I2C2
IEEE1500_2_OC
P
IPU1
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
PI_L3CLK
IPU1_GFCLK
Int
Func
Func
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Int
Func
Int
Func
Int & Func
Int & Func
L3_INSTR
L3_CLK
Int
L4_CFG
L4_CFG_CLK
Int
L4_PER1
L4_PER1_CLK
Int
L4_PER2
L4_PER2_CLK
Int
L4_PER3
L4_PER3_CLK
Int
L4_WKUP
L4_WKUP_CLK
Int
MAILBOX1
MAILBOX1_FLCK
Int
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock
Name
PLL / OSC /
Source Clock
Name
DDR
EMIF_PHY_GCLK EMIF_PHY_GCLK
266
EMIF_L3_GICLK CORE_X2_CLK
266
L3_EOCP_GICLK
-
532
EMIF_PHY_GCLK EMIF_PHY_GCLK
266
EMIF_DLL_GCLK
133
L4_ICLK
L3_ICLK
EVE_FCLK
EVE_GFCLK
EVE_GCLK
EVE_GFCLK
266
GMAC_RFT_CLK
L3_ICLK
SYS_CLK1
125
GMAC_MAIN_CLK GMAC_250M_CLK
250
GMII_250MHZ_CL GMII_250MHZ_CL
K
K
5
RGMII_5MHZ_CLK RGMII_5MHZ_CLK
50
RMII_50MHZ_CLK GMAC_RMII_HS_
CLK
38.4
WKUPAON_GICL
SYS_CLK1
K
0.032
WKUPAON_SYS_ WKUPAON_32K_
GFCLK
GFCLK
133
L4PER_L3_GICLK CORE_X2_CLK
0.032
GPIO_GFCLK FUNC_32K_CLK
133
L4PER_L3_GICLK CORE_X2_CLK
0.032
GPIO_GFCLK FUNC_32K_CLK
133
L4PER_L3_GICLK CORE_X2_CLK
0.032
GPIO_GFCLK FUNC_32K_CLK
266
L3MAIN1_L3_GIC CORE_X2_CLK
LK
133
L4PER_L3_GICLK CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
133
L4PER_L3_GICLK CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L3INIT_L3_GICLK CORE_X2_CLK
IPU_CLK
L3_CLK
133
133
133
133
38.4
133
IPU1_GFCLK
SYS_CLK1
CORE_IPU_ISS_B
OOST_CLK
L3INSTR_L3_GICL CORE_X2_CLK
K
L4CFG_L3_GICLK CORE_X2_CLK
L4PER_L3_GICLK CORE_X2_CLK
L4PER2_L3_GICL CORE_X2_CLK
K
L4PER3_L3_GICL CORE_X2_CLK
K
WKUPAON_GICL
K
SYS_CLK1
L4CFG_L3_GICLK CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_DDR
DPLL_CORE
-
DPLL_DDR
DPLL_DDR
CORE_CLK
DPLL_DSP
DPLL_EVE
DPLL_CORE
OSC0
DPLL_GMAC
DPLL_GMAC
RMII_CLK
DPLL_GMAC
OSC0
OSC0
DPLL_CORE
OSC0
DPLL_CORE
OSC0
DPLL_CORE
OSC0
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
OSC0
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
DPLL_CORE
82
Specifications
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