TDA3MV Datasheet, PDF (145/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 7-20. Timing Requirements for SPI - Master Mode (continued)
NO.
SM8
PARAMETER
t_d(CS-SPICLK)
DESCRIPTION
Delay time, spi_cs[x] active to spi_sclk first edge ⁽¹⁾
MODE
MIN
MASTER B-4.2 (5)
_PHA0
(4)
MAX
UNIT
ns
MASTER A-4.2 (6)
ns
_PHA1
(4)
SM9 t_d(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive ⁽¹⁾
MASTER A-4.2 (6)
ns
_PHA0
(4)
MASTER B-4.2 (5)
ns
_PHA1
(4)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) P = SPICLK period.
(4) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(5) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(6) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(7) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
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Timing Requirements and Switching Characteristics 145
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