TDA3MV Datasheet, PDF (13/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
BALL NUMBER [1]
BALL NAME [2]
N5
dcan1_tx
F2
G1
AB13
AB10
AA10
G2
F1
N1
E3
U4
C1
D3
R4
T4
N3
T2
N2
T1
U1
D1
R3
ddr1_casn
ddr1_ck
ddr1_dqm_ecc
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_nck
ddr1_rasn
ddr1_rst
ddr1_wen
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
Table 4-2. Ball Characteristics⁽¹⁾ (continued)
SIGNAL NAME [3]
dcan1_tx
gpio4_9
Driver off
ddr1_casn
ddr1_ck
ddr1_dqm_ecc
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_nck
ddr1_rasn
ddr1_rst
ddr1_wen
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
MA/LX/LA MUXMODE
[4]
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
I/O
REL. VOLTAGE
MUXMODE VALUE [10]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
IO
PU
PU
15
1.8/3.3
vddshv1 Yes
Dual
PU/PD
14
IO
Voltage
LVCMOS
15
I
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive clk 0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PU
PU
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
O
PD
drive clk 0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 0
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
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Terminal Configuration and Functions
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