TDA3MV Datasheet, PDF (205/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
8.7.3.2 Compatible JEDEC LPDDR2 Devices
Table 8-14 shows the supported LPDDR2 device configurations which are compatible with this interface.
Table 8-14. Compatible JEDEC LPDDR2 Devices (Per Interface)
NO.
PARAMETER
1 JEDEC LPDDR2 device speed grade
2 JEDEC LPDDR2 device bit width
3 JEDEC LPDDR2 device count
CONDITION
t_{c(DDR_CK)} and t_{c(DDR_NCK)}
MIN
LPDDR2-667
x16
1
MAX UNIT
x32 Bits
1 Devices
8.7.3.3 LPDDR2 PCB Stackup
Table 8-15 shows the minimum stackup requirements. Additional layers may be added to the PCB
stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference
performance, or to reduce the size of the PCB footprint.
Table 8-15. Six-Layer PCB Stackup Suggestion
LAYER
1
2
3
4
5
6
TYPE
Signal
Plane
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
Signal routing
Split power plane
Ground
Bottom signal routing
PCB stackup specifications for LPDDR2 interface are listed in Table 8-16.
Table 8-16. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
MAX UNIT
1 PCB routing and plane layers
6
2 Signal routing layers
3
3 Full ground reference layers under LPDDR2 routing region⁽¹⁾
1
4 Full vdds_ddr power reference layers under the LPDDR2 routing region⁽¹⁾
1
5 Number of reference plane cuts allowed within LPDDR2 routing region⁽²⁾
0
6 Number of layers between LPDDR2 routing layer and reference plane⁽³⁾
0
7 PCB routing feature size
4
mils
8 PCB trace width, w
9 PCB BGA escape via pad size⁽⁴⁾
4
mils
18
20 mils
10 PCB BGA escape via hole size
11 Single-ended impedance, Zo⁽⁵⁾
12 Impedance control⁽⁶⁾⁽⁷⁾
Zo-5
8
mils
50
75 Ω
Zo
Zo+5 Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the LPDDR2 routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Zo is the nominal singled-ended impedance selected for the PCB.
(6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(7) Tighter impedance control is required to ensure flight time skew is minimal.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 205
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