TDA3MV Datasheet, PDF (144/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
SIGNALS
uart3_ctsn
BALL
Table 7-19. UART1-3 IOSETs (continued)
IOSET1
MUX
BALL
N4
IOSET2
MUX
1
BALL
U6
IOSET3
MUX
1
7.12 Multichannel Serial Peripheral Interface (McSPI)
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
• Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– SPI configuration per channel. This means, clock definition, polarity enabling and word width
• Power management through wake-up capabilities
• Programmable timing control between chip select and external clock generation
• Built-in FIFO available for a single channel.
• Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
Table 7-20, Figure 7-23 and Figure 7-24 present Timing Requirements for McSPI - Master Mode.
NO.
SM1
PARAMETER
t_c(SPICLK)
SM2 t_w(SPICLKL)
SM3 t_w(SPICLKH)
SM4
SM5
SM6
t_{su(MISO-SPICLK)}
t_{h(SPICLK-MISO)}
t_{d(SPICLK-SIMO)}
SM7 t_d(CS-SIMO)
Table 7-20. Timing Requirements for SPI - Master Mode
DESCRIPTION
Cycle time, spi_sclk ^{(1) (2)}
Typical Pulse duration, spi_sclk low ⁽¹⁾
Typical Pulse duration, spi_sclk high ⁽¹⁾
Setup time, spi_d[x] valid before spi_sclk active edge ⁽¹⁾
Hold time, spi_d[x] valid after spi_sclk active edge ⁽¹⁾
Delay time, spi_sclk active edge to spi_d[x] transition ⁽¹⁾
Delay time, spi_cs[x] active edge to spi_d[x] transition
MODE
SPI1/2/3/
4
SPI1/2/4
SPI3
MIN
20.8
0.5*P-1
(3)
0.5*P-1
(3)
2.29
2.67
-3.57
-3.57
MAX
3.57
3.57
3.57
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
144 Timing Requirements and Switching Characteristics
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