TDA3MV Datasheet, PDF (167/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 1000Mbps operation is not supported.
(3) RGMII1 1000Mbps operation is not supported.
rgmiin_txc^(A)
[internal delay enabled]
1
4
2
3
4
5
rgmiin_txd[3:0]^(B)
1st Half-byte 2nd Half-byte
6
rgmiin_txctl^(B)
TXEN
TXERR
SPRS91v_GMAC_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-36. GMAC Transmit Interface Timing RGMIIn operation
7.17 SDIO Controller
MMC interface is compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it
supports the following applications:
• MMC 4-bit data, SD Default speed, SDR
• MMC 4-bit data, SD High speed, SDR
• MMC 4-bit data, UHS-I SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle
• MMC 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
NOTE
For more information, see the SDIO Controller chapter of the Device TRM.
7.17.1 MMC, SD Default Speed
Figure 7-37, Figure 7-38, and Table 7-42 through Table 7-43 present Timing requirements and Switching
characteristics for MMC - SD and SDIO Default speed in receiver and transmiter mode.
Table 7-42. Timing Requirements for MMC - Default Speed Mode
NO. PARAMETER
DS5
DS6
DS7
DS8
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
(1) i in [i:0] = 3
DESCRIPTION
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
MIN
5.11
20.46
5.11
20.46
MAX
UNIT
ns
ns
ns
ns
Table 7-43. Switching Characteristics for MMC - SD/SDIO Default Speed Mode
NO.
DS0
DS1
PARAMETER
fop(clk)
t_w(clkH)
DESCRIPTION
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
MIN
0.5*P-
0.270
MAX
24
UNIT
MHz
ns
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 167
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