TDA3MV Datasheet, PDF (184/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
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5. Place all voltage and gnd plane vias "as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a "Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the CORE power domain (vdd) has yielded the Impedance vs Frequency
responses shown in Section 8.3.7.2, vdd Example Analysis.
8.2.5 System ESD Generic Guidelines
8.2.5.1 System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in Figure 8-10) from connector to external protection because the interconnect may see between 15-
A to 30-A current in a short period of time during the ESD event.
Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Signal
VCC
Protected
circuit
Interconnection
inductance
Stub
inductance
vcc
Minimize such
inductance by
optimizing layout
Ground
inductance
Stub
inductance
External
protection
VCC
Signal
ESD
strike
Keep distance
between protected
circuit and external
protection
Keep external
protection closed by
connector
SPRS91v_PCB_ESD_01
Figure 8-10. Placement Recommendation for an ESD External Protection
184 Applications, Implementation, and Layout
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