TDA3MV Datasheet, PDF (56/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
4.4.7 Imaging Subsystem (ISS)
NOTE
For more information, see the Imaging Subsystem of the device TRM.
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CAUTION
The IO timings provided in Section 7 Timing Requirements and Switching
Characteristics are only valid if signals within a single IOSET are used. The
IOSETs are defined in Table 7-6.
Table 4-10. CSI 2 Signal Descriptions
SIGNAL NAME DESCRIPTION
csi2_0_dx0
Serial Differential data/clock positive input - lane 0 (position 1)
csi2_0_dy0
Serial Differential data/clock negative input - lane 0 (position 1)
csi2_0_dx1
Serial Differential data/clock positive input - lane 1 (position 2)
csi2_0_dy1
Serial Differential data/clock negative input - lane 1 (position 2)
csi2_0_dx2
Serial Differential data/clock positive input - lane 2 (position 3)
csi2_0_dy2
Serial Differential data/clock negative input - lane 2 (position 3)
csi2_0_dx3
Serial Differential data/clock positive input - lane 3 (position 4)
csi2_0_dy3
csi2_0_dx4
csi2_0_dy4
Serial Differential data/clock negative input - lane 3 (position 4)
Serial Differential data positive input only - lane 4 (position 5) ⁽¹⁾
Serial Differential data negative input only - lane 4 (position 5) ⁽¹⁾
(1) Lane 4 (position 5) supports only data. For more information see Imaging Subsystem of the device TRM.
TYPE
I
I
I
I
I
I
I
I
I
I
4.4.8 External Memory Interface (EMIF)
BALL
A11
B11
A12
B12
A13
B13
A15
B15
A16
B16
NOTE
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
NOTE
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-11,
EMIF Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type of
SDRAM memories.
Table 4-11. EMIF Signal Descriptions
SIGNAL NAME
ddr1_cke0
ddr1_nck
ddr1_odt0
ddr1_rasn
ddr1_rst
ddr1_wen
ddr1_csn0
ddr1_ck
DESCRIPTION
EMIF1 Clock Enable 0
EMIF1 Negative Clock
EMIF1 On-Die Termination for Chip Select 0
EMIF1 Row Address Strobe; When LPDDR2 is used this signal functions as to
ddr1_ca0
EMIF1 Reset output
EMIF1 Write Enable; When LPDDR2 is used this signal functions as ddr1_ca2
EMIF1 Chip Select 0
EMIF1 Clock
TYPE
O
O
O
O
O
O
O
O
BALL
F3
G2
P2
F1
N1
E3
B2
G1
56
Terminal Configuration and Functions
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