TDA3MV Datasheet, PDF (209/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
LPDDR2
interface
i = 0, 1, 2, 3
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
DQ0 - DQ3 represent data bytes 0 - 3.
DQLMXi
DQi
DQLMYi
SPRS917_LPDDR2_10
There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16-
bit interface. Each DQLM is the longest Manhattan distance of the byte.
Figure 8-31. DQLM for LPDDR2 Interface
Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 8-20.
Table 8-20. DQS[x] and DQ[x] Routing Specification⁽¹⁾⁽²⁾
NO.
1 DQ0 nominal length⁽³⁾⁽⁴⁾
2 DQ1 nominal length⁽³⁾⁽⁵⁾
3 DQ2 nominal length ⁽³⁾⁽⁶⁾
4 DQ3 nominal length ⁽³⁾⁽⁷⁾
5 DQ[x] skew⁽⁸⁾
PARAMETER
MIN
TYP
MAX UNIT
DQLM0 mils
DQLM1 mils
DQLM2 mils
DQLM3 mils
10 ps
6 DQS[x] skew
5 ps
7 Via count per each trace in DQ[x], DQS[x]
2
8 Via count difference across a given DQ[x], DQS[x]
0
9 DQS[x]-to-DQ[x] skew⁽⁸⁾⁽⁹⁾
10 ps
10 Center-to-center DQ[x] to other LPDDR2 trace spacing^(10)(11)
4
w
11 Center-to-center DQ[x] to other DQ[x] trace spacing^(10)(12)
3
w
12 DQS[x] center-to-center spacing⁽¹³⁾
13 DQS[x] center-to-center spacing to other net⁽¹⁰⁾
4
w
(1) DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net
classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) DQLM2 is the longest Manhattan length for the DQ2 net class.
(7) DQLM3 is the longest Manhattan length for the DQ3 net class.
(8) Length matching is only done within a byte. Length matching across bytes is not required.
(9) Each DQS clock net class is length matched to its associated DQ signal net class.
(10) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.
(11) Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class.
(12) This applies to spacing within same DQ[x] signal net class.
(13) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-
ended impedance.
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Applications, Implementation, and Layout 209
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