TDA3MV Datasheet, PDF (174/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
TCK
1
1a
1b
2
TDO
3
4
TDI/TMS
Figure 7-45. JTAG Timing
SPRS91v_JTAG_01
Table 7-54, Table 7-55 and Figure 7-46 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-54. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
1a
1b
3
4
PARAMETER
t_c(TCK)
t_w(TCKH)
t_w(TCKL)
t_su(TDI-TCK)
t_su(TMS-TCK)
t_h(TCK-TDI)
t_h(TCK-TMS)
DESCRIPTION
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
62.29
24.92
24.92
6.23
6.23
31.15
31.15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 7-55. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
5
PARAMETER
t_d(TCK-RTCK)
6
t_c(RTCK)
7
t_w(RTCKH)
8
t_w(RTCKL)
DESCRIPTION
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the ARM is in the scan chain, the delay
time is a function of the ARM functional clock).
Cycle time, RTCK
Pulse duration, RTCK high (40% of tc)
Pulse duration, RTCK low (40% of tc)
MIN
0
62.29
24.92
24.92
MAX
27
UNIT
ns
ns
ns
ns
TCK
5
6
7
8
RTCK
Figure 7-46. JTAG With RTCK Timing
SPRS91v_JTAG_02
174 Timing Requirements and Switching Characteristics
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