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TDA3MV Datasheet, PDF (193/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0
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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
8.3.7 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_dspeve key processor power domain.
NOTE
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
8.3.7.1 Example Stack-up
Layer Assignments:
• Layer Top: Signal and Segmented Power Plane
– Processor and PMIC components placed on Top-side
• Layer 2: Gnd Plane1
• Layer 3: Signals
• Layer n: Power Plane1
• Layer n+1: Power Plane 2
• Layer n+2: Signal
• Layer n+3: Gnd Plane2
• Layer Bottom: Signal and Segmented Power Planes
– Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
• ½ oz for all signal layers.
• 1-2oz for all power plane for improved PCB heat spreading
8.3.7.2 vdd_dspeve Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 33mΩ per Table 8-3 and (7).
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.5nH per Table 8-3 and (7) (ESL NOT included).
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 54mΩ per Table 8-3 and (7).
Table 8-7. Example PCB vdd_dspeve PI Analysis Summary
Parameter
OPP
Clocking Rate
Voltage Level
Max Current Draw
Max Effective Resistance: Power
Inductor Segment Total Reff
Max Loop Inductance
Impedance Target
Recommendation
OPP_NOM
500 MHz
1V
1A
13 mΩ
< 2.5 nH
54 mΩ for F < 20 MHz
Example PCB
1V
1A
11.4mΩ
0.73 - 1.58 nH
28.8 mΩ for F < 20MHz
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 193
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