TDA3MV Datasheet, PDF (198/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
• Propagation delays and matching:
– A to C = C to D = E to F
– Matching skew: < 60pS
– A to B < 450pS
– B to C = as small as possible (<60pS)
A
R1
0 Ω*
qspi1_sclk
D
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Locate both R2 resistors
close together near the QSPI device
B
C
R2
10 Ω
R2
10 Ω
QSPI device
clock input
qspi1_rtclk
E
F
qspi1_d[x], qspi1_cs[y]
QSPI device
IOx, CS#
SPRS906_PCB_QSPI_01
Figure 8-19. QSPI Interface High Level Schematic Mode 0 (POL=0, PHA=0)
NOTE
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
8.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
• The qspi1_rtclk input can be left unconnected.
• The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
• The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be
< 450pS (~7cm as stripline or ~8cm as microstrip).
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-20.
• Propagation delays and matching:
– A to C = E to F.
– Matching skew: < 60Ps
– A to B < 450pS
198 Applications, Implementation, and Layout
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