TDA3MV Datasheet, PDF (139/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
The device has eight GP timers: TIMER1 through TIMER8.
• TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating
system and it belongs to the PD_WKUPAON domain.
• TIMER2 through TIMER8 belong to the PD_COREAON module.
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the
clock source at the power, reset, and clock management (PRCM) module level.
Each timer provides an interrupt through the device IRQ_CROSSBAR.
Each timer is connected to an external pin by their PWM output or their event capture input pin (for
external timer triggering).
7.9.1 GP Timer Features
The following are the main features of the GP timer controllers:
• Level 4 (L4) slave interface support:
– 32-bit data bus width
– 32- or 16-bit access supported
– 8-bit access not supported
– 10-bit address bus width
– Burst mode not supported
– Write nonposted transaction mode supported
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Compare and capture modes
• Autoreload mode
• Start and stop mode
• Programmable divider clock source (2_n, where n = [0:8])
• Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
• Dedicated GP output signal for using the TIMERi_GPO_CFG signal
• On-the-fly read/write register (while counting)
• 1-ms tick with 32.768-Hz functional clock generated (only TIMER1)
7.10 Inter-Integrated Circuit Interface (I2C)
The device includes 2 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
NOTE
Note that, I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not
supported
NOTE
Inter-integrated circuit i ( i=1 to 2) module is also referred to as I2Ci.
NOTE
For more information, see the Multimaster I2C Controller section of the Device TRM.
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Timing Requirements and Switching Characteristics 139
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