TDA3MV Datasheet, PDF (14/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
BALL NUMBER [1]
BALL NAME [2]
U2
C3
R2
V1
B3
A3
D2
F3
B2
AA6
AA8
Y8
AA7
AB4
Y5
AA4
Y6
AA18
Y21
AA21
Y22
AA19
AB20
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_cke0
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
Table 4-2. Ball Characteristics⁽¹⁾ (continued)
SIGNAL NAME [3]
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_cke0
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
MA/LX/LA MUXMODE
[4]
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
I/O
REL. VOLTAGE
MUXMODE VALUE [10]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 0
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
O
PD
drive 1
0
1.35/1.5/1.8 vdds_ddr2 NA
LVCMOS PUx/PDy
(OFF)
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr1 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
0
IO
PD
PD
0
1.35/1.5/1.8 vdds_ddr3 NA
LVCMOS PUx/PDy
DDR
14
Terminal Configuration and Functions
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