TDA3MV Datasheet, PDF (128/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
gpmc_clk
gpmc_csi
gpmc_a[27:1]
gpmc_ben1
gpmc_ben0
gpmc_advn_ale
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
gpio6_16.clkout0
F1
F1
F0
F2
F4
Address
F6
F6
F8 F8
F20
F14
F14
D0
F22
F3
F18
F17
F17
F17
F17
F17
F17
F9
F15 F15 F15
D1 D2
D3
F21
F23
F23
GPMC_06
Figure 7-9. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)⁽¹⁾⁽²⁾
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
7.8.2
GPMC/NOR Flash Interface Asynchronous Timing
Table 7-11 and Table 7-12 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-10, Figure 7-11, Figure 7-12, Figure 7-13,
Figure 7-14 and Figure 7-15).
NO.
FA5
FA20
FA21
-
-
Table 7-11. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
PARAMETER
t_acc(DAT)
t_{acc1-pgmode(DAT)}
t_{acc2-pgmode(DAT)}
t_su(DV-OEH)
t_h(OEH-DV)
DESCRIPTION
MIN
Data Maximum Access Time (GPMC_FCLK cycles)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
1.9
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
1
MAX
H ⁽¹⁾
P ⁽²⁾
H ⁽¹⁾
UNIT
cycles
cycles
cycles
ns
ns
128 Timing Requirements and Switching Characteristics
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