TDA3MV Datasheet, PDF (116/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
Table 7-5 and Figure 7-3 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 7-5. DPI Video Output 1 Switching Characteristics ⁽¹⁾⁽²⁾
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
D1
t_c(clk)
D2
t_w(clkL)
D3
t_w(clkH)
D5
t_d(clk-ctlV)
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
6.73
ns
P*0.5-1
ns
P*0.5-1
ns
DPI1
-1.33
1.01
ns
D6
t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI1
-1.33
1.01
ns
(1) P = output vout1_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D1
D3
D4
vouti_clk
D6
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
vouti_fld
odd
even
SWPS049-018
Figure 7-3. DPI Video Output ^(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vout1_hsync and vout1_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vout1_clk frequency can be configured, refer to the DSS section of the device TRM.
116 Timing Requirements and Switching Characteristics
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