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| TDA3MV Datasheet, PDF (227/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0 | |||
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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C â JUNE 2016 â REVISED JULY 2017
Table 8-38. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
MAX
UNIT
PS1
PCB routing/plane layers
6
PS2
Signal routing layers
3
PS3
Full ground reference layers under DDR3 routing region(1)
1
PS4
Full 1.5-V power reference layers under the DDR3 routing region(1)
1
PS5
Number of reference plane cuts allowed within DDR routing region(2)
0
PS6
Number of layers between DDR3 routing layer and reference plane(3)
0
PS7
PCB routing feature size
4
Mils
PS8
PCB trace width, w
4
Mils
PS9
PS10
Single-ended impedance, Zo
Impedance control(5)
50
75
â¦
Z-5
Z
Z+5
â¦
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
8.9.2.6 Placement
Figure 8-47 shows the required placement for the processor as well as the DDR3 devices. The
dimensions for this figure are defined in Table 8-39. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3
devices are omitted from the placement.
x1
y2
DDR3
Controller
y2
Three Devices
Figure 8-47. Placement Specifications
SPRS91v_PCB_DDR3_04
Copyright © 2016â2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 227
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