TDA3MV Datasheet, PDF (169/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
(1) i in [i:0] = 3
Table 7-45. Switching Characteristics for MMC - SD/SDIO High Speed Mode
NO.
HS1
HS2H
PARAMETER
fop(clk)
t_w(clkH)
DESCRIPTION
Operating frequency, mmc_clk
Pulse duration, mmc_clk high
HS2L t_w(clkL)
Pulse duration, mmc_clk low
HS5
HS6
t_d(clkL-cmdV)
t_d(clkL-dV)
Delay time, mmc_clk falling clock edge to mmc_cmd transition
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition
(1) P = output mmc_clk period in ns
(2) i in [i:0] = 3
MIN
0.5*P-
0.270
0.5*P-
0.270
-7.6
-7.6
MAX
48
3.6
3.6
UNIT
MHz
ns
ns
ns
ns
mmc_clk
mmc_cmd
mmc_dat[3:0]
HS1
HS2L
HS3
HS7
HS2H
HS4
HS8
Figure 7-39. MMC/SD/SDIOj in - High Speed - Receiver Mode
SPRS91v_MMC_03
mmc_clk
mmc_cmd
mmc_dat[3:0]
HS1
HS2H
HS2L
HS5
HS6
HS5
HS6
Figure 7-40. MMC/SD/SDIOj in - High Speed - Transmiter Mode
SPRS91v_MMC_04
7.17.3 MMC, SD and SDIO SDR12 Mode
Figure 7-41, Figure 7-42, and Table 7-46, through Table 7-47 present Timing requirements and Switching
characteristics for MMC - SD and SDIO SDR12 in receiver and transmiter mode.
NO. PARAMETER
SDR125
SDR126
SDR127
SDR128
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
Table 7-46. Timing Requirements for MMC - SDR12 Mode
DESCRIPTION
Setup time, mmc_cmd valid before mmc_clk rising clock edge
Hold time, mmc_cmd valid after mmc_clk rising clock edge
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge
MIN
25.99
1.6
25.99
1.6
MAX
UNIT
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 169
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