TDA3MV Datasheet, PDF (191/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
• LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
"theoretical shorted” applied across the Processor’s supply inputs to ground reference.
• Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
• Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
Table 8-3. Recommended PDN and Decoupling Characteristics ^{(1)(2)(3)(4)(5)}
PDN Analysis: Static
Dynamic
Number of Recommended Decoupling Capacitors per
Supply
Supply
Max R_eff Dec. Cap.
(7)
Max LL^{(8) (6)}
[mΩ]
[nH]
Max
Impedance
[mΩ]
Frequency
range
of Interest
[MHz]
100
nF⁽⁶⁾
220
nF
470
nF
1μF 2.2 μF 4.7 μF 10 μF 22 μF
vdd_dspeve
33
2.5
54
≤20
6
1
1
1
1
1
1
vdd
83
2
87
≤50
6
1
1
1
1
1
vdds_ddr1,
vdds_ddr2,
33
2.5
200
≤100
8
4
2
2
1
vdds_ddr3
cap_vddram_cor
e1
N/A
6
N/A
N/A
1
cap_vddram_cor
e2
N/A
6
N/A
N/A
1
cap_vddram_dsp
eve
N/A
6
N/A
N/A
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Electrical Characteristics
chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Electrical Characteristics chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Total R_eff from PMIC output to remote sensing feedback point located as close to the Device's point of load as possible.
(8) Maximum Loop Inductance for decoupling capacitor.
8.3.5 Power Supply Mapping
TPS65917 is a Power management IC (PMIC) that can be used for the Device design. TI is now
investigating an optimized solution for high power use cases so the TPS65917 is subject to change. An
alternate dual converter power solution using LP8732Q and LP8733Q are recommended. TI requires the
use of one of these PMIC solutions for the following reasons:
• TI has validated its use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
• Support for power sequencing requirements (refer to Section 5.10 Power Sequencing)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
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Applications, Implementation, and Layout 191
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