TDA3MV Datasheet, PDF (94/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 5-15. LVCMOS CSI2 DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
Bottom Balls: A11 / B11 / A12 / B12 / A13 / B13 / A15 / B15 / A16 / B16
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
V_IH
Input high-level voltage
880
1350
mV
V_IL
Input low-level voltage
550
mV
V_ITH
Input high-level threshold
880
mV
V_ITL
Input low-level threshold
550
mV
V_HYS
Input hysteresis
25
mV
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
V_IH
Input high-level voltage
V_IL
Input low-level voltage
V_ITH
Input high-level threshold
V_ITL
Input low-level threshold
V_HYS
Input hysteresis
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
880
mV
300
mV
880
mV
300
mV
25
mV
V_IDTH
V_IDTL
V_IDMAX
V_IHHS
V_ILHS
V_CMRXDC
Z_ID
Differential input high-level threshold
Differential input low-level threshold
Maximum differential input voltage
Single-ended input high voltage
Single-ended input low voltage
Differential input common-mode voltage
Differential input impedance
70
mV
–70
mV
270
mV
460
mV
–40
mV
70
330
mV
80
100
125
Ω
(1) V_ITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. V_ITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, V_HYST. V_HYST is the difference
between the V_ITH threshold and the V_ITL threshold.
(4) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mV_PP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VOD_MAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: V_CMRX = (V_X + V_Y) / 2.
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.
5.7.7 Dual Voltage LVCMOS DC Electrical Characteristics
Table 5-16 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.
PARAMETER
1.8-V Mode
V_IH
V_IL
V_HYS
V_OH
V_OL
I_DRIVE
I_IN
Table 5-16. Dual Voltage LVCMOS DC Electrical Characteristics
DESCRIPTION
MIN
NOM
MAX
UNIT
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Output high-level threshold (I_OH = 2 mA)
Output low-level threshold (I_OL = 2 mA)
Pin Drive strength at PAD Voltage = 0.45V or VDDS-
0.45V
Input current at each I/O pin
0.65*VDDS
100
VDDS-0.45
6
V
0.35*VDDS
V
mV
V
0.45
V
mA
16
µA
94
Specifications
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