TDA3MV Datasheet, PDF (113/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
7.4 Video Input Ports (VIP)
The device includes 1 Video Input Ports (VIP).
Table 7-2, Figure 7-1 and Figure 7-2 present timings and switching characteristics of the VIPs
Table 7-2. Timing Requirements for VIP ⁽¹⁾⁽²⁾
NO.
PARAMETER
DESCRIPTION
V1
t_c(CLK)
Cycle time, vinx_clki⁽³⁾⁽⁵⁾
V2
t_w(CLKH)
Pulse duration, vinx_clki high⁽³⁾⁽⁵⁾
V3
t_w(CLKL)
Pulse duration, vinx_clki low⁽³⁾⁽⁵⁾
V4 t_{su(CTL/DATA-CLK)} Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition ^(3)(4)(5)
V5 t_{h(CLK-CTL/DATA)} Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition^(3)(4)(5)
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a and 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b;
n = 0 to 23 when x = 1a and 2a;
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
MIN
5.99 ⁽¹⁾
0.45*P ⁽²⁾
0.45*P ⁽²⁾
2.52
-0.05
MAX
V2
V3
V1
vinx_clki
UNIT
ns
ns
ns
ns
ns
Figure 7-1. Video Input Ports Clock Signal
SPRS91v_VIP_01
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
vinx_d[23:0]/sig
V5
V4
Figure 7-2. Video Input Ports Timings
SPRS8xx_VIP_02
CAUTION
The IO timings provided in this section are only valid for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in Table 7-3
and Table 7-4.
In Table 7-3 and Table 7-4 are presented the specific groupings of signals (IOSET) for use with vin1a,
vin1b, vin2a and vin2b.
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Timing Requirements and Switching Characteristics 113
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