TDA3MV Datasheet, PDF (119/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
NOTE
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
Table 7-8. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load
NO.
F0
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F14
F15
F17
F18
F19
F20
F23
PARAMETER
t_c(clk)
t_d(clkH-nCSV)
t_{d(clkH-nCSIV)}
t_d(ADDV-clk)
t_{d(clkH-ADDIV)}
t_d(nBEV-clk)
t_{d(clkH-nBEIV)}
t_d(clkH-nADV)
t_{d(clkH-nADVIV)}
t_d(clkH-nOE)
t_{d(clkH-nOEIV)}
t_d(clkH-nWE)
t_d(clkH-Data)
t_d(clkH-nBE)
t_w(nCSV)
t_w(nBEV)
t_w(nADVV)
t_d(CLK-GPIO)
DESCRIPTION
Cycle time, output clock gpmc_clk period ⁽¹²⁾
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid ⁽¹⁴⁾
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus
invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_wen transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus
transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
Pulse duration, gpmc_ben[1:0] low
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout0 transition ⁽¹³⁾
MIN
11.3
F-0.8
E-0.8
B-0.8
-0.8
B-3.8
D-0.4
G-0.8
D-0.8
H-0.8
E-0.8
I-0.8
J-1.1
J-1.1
A
C
K
1.2
MAX
F+3.1
E+3.1
B+3.1
B+1.1
D+1.1
G+3.1
D+3.1
H+2.1
E+2.1
I+3.1
J+3.92
J+3.8
6.1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-9. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads
NO.
F12
F13
F21
F22
PARAMETER
t_su(dV-clkH)
t_h(clkH-dV)
t_{su(waitV-clkH)}
t_{h(clkH-waitV)}
DESCRIPTION
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
MIN
MAX
UNIT
2.5
ns
1.9
ns
2.5
ns
1.9
ns
Table 7-10. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads
NO.
F0
F2
F3
F4
F5
F6
F7
F8
F9
PARAMETER
t_c(clk)
t_d(clkH-nCSV)
t_{d(clkH-nCSIV)}
t_d(ADDV-clk)
t_{d(clkH-ADDIV)}
t_d(nBEV-clk)
t_{d(clkH-nBEIV)}
t_d(clkH-nADV)
t_{d(clkH-nADVIV)}
DESCRIPTION
Cycle time, output clock gpmc_clk period ⁽¹²⁾
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid ⁽¹⁴⁾
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus
invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition ⁽¹⁴⁾
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid ⁽¹⁴⁾
MIN
MAX
15.04
F+0.7 (6) F+6.1 (6)
E+0.7 (5) E+6.1 (5)
B+0.7 (2) B+6.1 (2)
0.7
B-4.9 B+0.4
D-0.4 D+4.9
G+0.7 (7) G+6.1 (7)
D+0.7 (4) D+6.1 (4)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 119
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