TDA3MV Datasheet, PDF (58/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 4-11. EMIF Signal Descriptions (continued)
SIGNAL NAME
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_dqsn_ecc
ddr1_dqs_ecc
DESCRIPTION
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 ECC Data Mask
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
Data strobe 0 invert
Data strobe 1 invert
Data strobe 2 invert
Data strobe 3 invert
EMIF1 ECC Complementary Data strobe
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
4.4.9 General-Purpose Memory Controller (GPMC)
BALL
U20
R22
V20
W22
U22
Y11
AA12
AA11
Y9
AA13
AB11
AA9
AB9
AB8
Y18
AB3
W21
AB13
AA5
AA20
W1
T21
AB5
Y20
W2
T22
AB10
AA10
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
Table 4-12. GPMC Signal Descriptions
SIGNAL NAME
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
DESCRIPTION
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
TYPE
IO
IO
IO
IO
BALL
E8
A7
F8
B7
58
Terminal Configuration and Functions
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