TDA3MV Datasheet, PDF (223/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

www.ti.com
TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
8.9.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
• Avoid crossing splits in the power plane.
• Use the widest trace that is practical between decoupling capacitors and memory module.
• Maintain a single reference
• Minimize ISI by keeping impedances matched.
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
• Keep the stub length as short as possible.
• Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
• Maintain a common ground reference for all bypass and decoupling capacitors.
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
8.9.2 DDR3 Board Design and Layout Guidelines
8.9.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-34 and
Figure 8-45.
Table 8-34. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
PARAMETER
MIN
MAX
UNIT
1 t_{c(DDR_CLK)}
Cycle time, DDR_CLK
1.875
2.5⁽¹⁾
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS91v_PCB_DDR3_01
Figure 8-45. DDR3 Memory Controller Clock Timing
8.9.2.2 DDR3 Device Combinations
There are several possible combinations of device counts and single- or dual-side mounting, Table 8-35
summarizes the supported device configurations.
NUMBER OF DDR3
DEVICES
1
2
2
2
2
3
3
Table 8-35. Supported DDR3 Device Combinations
DDR3 DEVICE WIDTH
(BITS)
1x16
2x8
2x16
2x16
1x16
2x8
2x16
ECC DEVICE WIDTH
(BITS)
-
-
-
-
1x8
1x8
1x8
MIRRORED?
N
Y⁽¹⁾
N
Y⁽¹⁾
N
N
N
DDR3 EMIF WIDTH
(BITS)
16
16
32
32
16
16
32
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 223
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA