TDA3MV Datasheet, PDF (200/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
8.5.2 CSI2 Board Design and Routing Guidelines
The MIPI D-PHY signals include the CSI2 camera serial interfaces to or from the Device.
For more information regarding the MIPI-PHY signals and corresponding balls, see Table 4-10, CSI2
Signal Descriptions.
For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).
In the next section, the PCB guidelines of the following differential interfaces are presented:
• CSI2_0 MIPI CSI-2 at 1.5 Gbps
Table 8-10 lists the MIPI D-PHY interface signals in the Device.
SIGNAL NAME
csi2_0_dx0
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
Table 8-10. MIPI D-PHY Interface Signals in the Device
BALL
A11
A12
A13
A15
A16
SIGNAL NAME
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
BALL
B11
B12
B13
B15
B16
8.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
8.5.2.1.1 General Guidelines
The general guidelines for the PCB differential lines are:
• Differential trace impedance Z₀ = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)
• Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30
cm with common FR4 PCB and flex materials.
NOTE
Longer interconnect length can be supported at the expense of detailed simulations of the
complete link including driver and receiver models.
The general rule of thumb for the space S = 2 × W is not designated (see Figure 8-18, Guard Illustration).
It is because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The
electrical performance will be checked with the frequency-domain specification. Even though the designer
does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain
specification.
Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed
differential implementation, the pairs must be loosely coupled.
8.5.2.1.2 Length Mismatch Guidelines
8.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
The guidelines of the length mismatch for CSI-2 are presented in Table 8-11.
Operating speed
UI (bit time)
Intralane skew
Table 8-11. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)
PARAMETER
TYPICAL VALUE
UNIT
1500
Mbps
667
ps
Have to satisfy mode-conversion S parameters⁽¹⁾
200 Applications, Implementation, and Layout
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