TDA3MV Datasheet, PDF (202/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
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Device
xi_oscj
xo_oscj
vssa_oscj
Crystal
Rd
(Optional)
C_f1
C_f2
(1) j in *_osc = 0 or 1
SPRS91v_PCB_CLK_OSC_03
Figure 8-22. Grounding Scheme for High-Frequency Clock
8.7 LPDDR2 Board Design and Layout Guidelines
8.7.1 LPDDR2 Board Designs
TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 8-12
and Figure 8-23.
Table 8-12. Switching Characteristics for LPDDR2 Memory Interface
NO.
PARAMETER
MIN
MAX UNIT
1 t_{c(DDR_CK)}
Cycle time, ddr1_ck and ddr1_nck
7.52
3.00⁽¹⁾
ns
(1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The
device has only been tested per the limits published in this table.
1
ddr1_ck
ddr1_nck
SPRS917_LPDDR2_01
Figure 8-23. LPDDR2 Memory Interface Clock Timing
8.7.2 LPDDR2 Device Configurations
There is signal device configuration supported, supporting either 32b or 16b data widths. Table 8-13 lists
all the supported configuration.
NUMBER OF LPDDR2
DEVICES
1
Table 8-13. Supported LPDDR2 Device Combinations
LPDDR2 DEVICE WIDTH (BITS)
32 / 16
MIRRORED?
N
LPDDR2 EMIF WIDTH (BITS)
32 / 16
202 Applications, Implementation, and Layout
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