TDA3MV Datasheet, PDF (231/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
8.9.2.9.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. These are returns for signal current, the signal via size may be used for these capacitors.
8.9.2.10 Net Classes
Table 8-42 lists the clock net classes for the DDR3 interface. Table 8-43 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-42. Clock Net Class Definitions
CLOCK NET CLASS processor PIN NAMES
CK
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
DQS2⁽¹⁾
DQS3⁽¹⁾
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
(1) Only used on 32-bit wide DDR3 memory systems.
Table 8-43. Signal Net Class Definitions
SIGNAL NET CLASS
ADDR_CTRL
ASSOCIATED CLOCK
NET CLASS
CK
DQ0
DQS0
DQ1
DQ2⁽¹⁾
DQ3⁽¹⁾
DQS1
DQS2
DQS3
(1) Only used on 32-bit wide DDR3 memory systems.
processor PIN NAMES
ddrx_ba[2:0], ddrx_a[15:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
8.9.2.11 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
8.9.2.12 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
8.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 8-44.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 231
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