TDA3MV Datasheet, PDF (206/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
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8.7.3.4 LPDDR2 Placement
Figure 8-25 shows the placement rules for the device as well as the LPDDR2 memory device. Placement
restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing
space.
X1
LPDDR2
DATA
LPDDR2
Y
ADDT_CTRL
SPRS917_LPDDR2_04
Figure 8-25. Placement Specifications
Table 8-17. Placement Specifications⁽¹⁾
NO.
1 X1 Offset⁽²⁾⁽³⁾
PARAMETER
MIN
MAX UNIT
900 mils
2 Y Offset
3 Clearance from non-LPDDR2 signal to LPDDR2 keepout region⁽⁴⁾⁽⁵⁾
200 mils
4
w
(1) LPDDR2 keepout region to encompass entire LPDDR2 routing area.
(2) Measurements from center of device to center of LPDDR2 device.
(3) Minimizing X1 and Y improves timing margins.
(4) w is defined as the signal trace width.
(5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground
plane.
8.7.3.5 LPDDR2 Keepout Region
The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2
keepout region is defined for this purpose and is shown in Figure 8-26. This region should encompass all
LPDDR2 circuitry and the region size varies with component placement and LPDDR2 routing. Non-
LPDDR2 signals should not be routed on the same signal layer as LPDDR2 signals within the LPDDR2
keepout region. Non-LPDDR2 signals may be routed in the region provided they are routed on layers
separated from LPDDR2 signal layers by a ground layer. No breaks should be allowed in the reference
ground or vdds_ddr power plane in this region. In addition, the vdds_ddr power plane should cover the
entire keepout region.
LPDDR2 Keepout Region
Encompasses Entire
LPDDR2 Routing Area
LPDDR2
DATA
LPDDR2
ADDT_CTRL
SPRS917_LPDDR2_05
Figure 8-26. LPDDR2 Keepout Region
206 Applications, Implementation, and Layout
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