TDA3MV Datasheet, PDF (243/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
A8^(A)
CACLMX
CACLMY
A8^(A)
A8^(A)
Rtt
A2
A3
AT
Vtt
=
SPRS91v_PCB_DDR3_27
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-70. CACLM for Two Address Loads on One Side of PCB
NO.
CARS31
CARS32
CARS33
CARS34
CARS35
CARS36
CARS37
CARS38
CARS39
CARS310
CARS311
CARS312
CARS313
CARS314
CARS315
CARS316
CARS317
CARS318
CARS319
CARS320
Table 8-44. CK and ADDR_CTRL Routing Specification⁽²⁾⁽³⁾
PARAMETER
MIN
TYP
A1+A2 length
A1+A2 skew
A3 length
A3 skew⁽⁴⁾
A3 skew⁽⁵⁾
A4 length
A4 skew
AS length
5
AS skew
1.3
AS+/AS- length
5
AS+/AS- skew
AT length⁽⁶⁾
75
AT skew⁽⁷⁾
14
AT skew⁽⁸⁾
CK/ADDR_CTRL trace length
Vias per trace
Via count difference
Center-to-center CK to other DDR3 trace spacing⁽⁹⁾
4w
Center-to-center ADDR_CTRL to other DDR3 trace spacing^(9)(10)
4w
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
3w
spacing⁽⁹⁾
MAX
500⁽¹⁾
29
125
6
6
125
6
17⁽¹⁾
14⁽¹⁾
12
1
1
1020
3⁽¹⁾
1⁽¹⁵⁾
UNIT
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
vias
vias
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Applications, Implementation, and Layout 243
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