TDA3MV Datasheet, PDF (153/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 7-24. Timing Requirements for QSPI (continued)
No PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
13
t_h(RTCLK-D)
Hold time, d[3:0] valid after falling rtclk edge
Default -0.1
ns
Timing
Mode,
Clock
Mode 0
t_h(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
Default
0.1
ns
Timing
Mode,
Clock
Mode 3
14
t_su(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk edge
Default 5.7-P (1)
ns
Timing
Mode,
Clock
Mode 3
15
t_h(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk edge
Default 0.1+P (1)
ns
Timing
Mode,
Clock
Mode 3
(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
PHA=1
cs
Q5
Q4
POL=1
sclk
Q1
Q3 Q2
Q7
d[0]
Q6
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q6
Q8
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
Figure 7-29. QSPI Write (Clock Mode 3)
SPRS85v_TIMING_OSPI1_03
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Timing Requirements and Switching Characteristics 153
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