TDA3MV Datasheet, PDF (155/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
7.14 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
The device has integrated 3 McASP modules (McASP1-McASP3) with:configure the desired virtual
• McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
• McASP3 module supporting 4 channels with independent TX/RX clock/sync domain
NOTE
For more information, see the Serial Communication Interface section of the Device TRM.
Table 7-26, Table 7-27, Table 7-28 and Figure 7-31 present Timing Requirements for McASP1 to
McASP3.
Table 7-26. Timing Requirements for McASP1 ⁽¹⁾
NO. PARAMETER DESCRIPTION
1
t_c(AHCLKX)
2
t_w(AHCLKX)
Cycle time, AHCLKX
Pulse duration, AHCLKX high or low
MODE
MIN
20
0.35P
(2)
3
t_c(ACLKRX)
Cycle time, ACLKR/X
4
t_w(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
20
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
15.258
Any Other Conditions 0.5R - 3
(3)
5 t _{su(AFSRX-ACLK)} Setup time, AFSR/X input valid before ACLKR/X
6 t _{h(ACLK-AFSRX)} Hold time, AFSR/X input valid after ACLKR/X
7
t _su(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
8
t _h(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In
Async Mode), and AXR
are all inputs
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
0.38R
(3)
18.5
3
0.5
0.4
18.5
3
0.5
0.4
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 155
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