TDA3MV Datasheet, PDF (135/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
gpmc_fclk
gpmc_clk
gpmc_csi
gpmc_a27
gpmc_a[10:1]
gpmc_ben0
gpmc_ben1
gpmc_advn_ale
gpmc_wen
gpmc_ad[15:0]
FA9
FA10
FA10
FA3
FA12
FA25
FA29
Valid Address (LSB)
FA1
Address (MSB)
FA0
FA0
FA27
FA28
Data OUT
gpmc_waitj
DIR
OUT
GPMC_12
Figure 7-15. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing⁽¹⁾
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
7.8.3 GPMC/NAND Flash Interface Asynchronous Timing
Table 7-13 and Table 7-14 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-16, Figure 7-17, Figure 7-18 and Figure 7-19).
Table 7-13. GPMC/NAND Flash Interface Timing Requirements⁽¹⁾
NO. PARAMETER
DESCRIPTION
GNF12
-
-
t_acc(DAT)
t_su(DV-OEH)
t_h(OEH-DV)
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
(1) J = AccessTime * (TimeParaGranularity + 1)
MIN
MAX
UNIT
J
cycles
1.9
ns
1
ns
Table 7-14. GPMC/NAND Flash Interface Switching Characteristics
NO.
-
-
GNF0
GNF1
PARAMETER
t_r(DO)
t_f(DO)
t_w(nWEV)
t_d(nCSV-nWEV)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
Fallling time, gpmc_ad[15:0] output data
Pulse duration, gpmc_wen valid time
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
MIN
0.447
0.43
B - 0.2 ⁽²⁾
MAX
4.067
4.463
A ⁽¹⁾
B + 2.0
(2)
UNIT
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 135
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