TDA3MV Datasheet, PDF (60/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 4-12. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_a16
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
O
F14
multiplexed mode
gpmc_a17
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
O
C14
multiplexed mode
gpmc_a18
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
O
F15
multiplexed mode
gpmc_a19
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
O
F16
multiplexed mode
gpmc_a20
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
O
multiplexed mode
AA14
gpmc_a21
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
O
multiplexed mode
AB14
gpmc_a22
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
O
U13
multiplexed mode
gpmc_a23
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
O
V13
multiplexed mode
gpmc_a24
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
O
Y13
multiplexed mode
gpmc_a25
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
O
multiplexed mode
W13
gpmc_a26
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
O
U11
multiplexed mode
gpmc_a27
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
O
V11
multiplexed mode
gpmc_cs0
GPMC Chip Select 0 (active low)
O
C10
gpmc_cs1
GPMC Chip Select 1 (active low)
O
E10
gpmc_cs2
GPMC Chip Select 2 (active low)
O
D10
gpmc_cs3
GPMC Chip Select 3 (active low)
O
A9
gpmc_cs4
GPMC Chip Select 4 (active low)
O
B9
gpmc_cs5
GPMC Chip Select 5 (active low)
O
F10
gpmc_cs6
GPMC Chip Select 6 (active low)
O
C8
gpmc_cs7
gpmc_clk⁽¹⁾
GPMC Chip Select 7 (active low)
GPMC Clock output
O
W6
IO
C12, D14, F14, F15
gpmc_advn_ale
GPMC address valid active low or address latch enable
O
F12
gpmc_oen_ren
GPMC output enable active low or read enable
O
A10
gpmc_wen
GPMC write enable active low
O
B10
gpmc_ben0
GPMC lower-byte enable active low
O
D12
gpmc_ben1
GPMC upper-byte enable active low
O
E12
gpmc_wait0
GPMC external indication of wait 0
I
D8
gpmc_wait1
GPMC external indication of wait 1
I
W7
(1) The gpio6_16.clkout0 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See Table 7-8 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load and Table 7-10
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads for timing information.
4.4.10 Timers
NOTE
For more information, see the Timers section of the device TRM.
60
Terminal Configuration and Functions
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