TDA3MV Datasheet, PDF (151/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 7-23. Switching Characteristics for QSPI (continued)
No PARAMETER
DESCRIPTION
Mode
MIN
MAX
UNIT
4
t_d(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0
Default -M*P-1 -M*P+1
ns
Timing (2) (3) (2) (3)
Mode
5
t_d(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge, CS3:0
Default N*P-1 (2) N*P+1
ns
Timing
(3)
(2) (3)
Mode
6
t_d(SCLK-D1)
Delay time, sclk falling edge to d[0] transition
Default
-1
1
ns
Timing
Mode
7
t_ena(CS-D1LZ)
8
t_dis(CS-D1Z)
9
t_d(SCLK-D1)
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
Delay time, sclk first falling edge to first d[0] transition
-P-3.5 -P+2.5
ns
-P-2.5 -P+2.0
ns
PHA=0 -1-P
-1-P
ns
Only,
Default
Timing
Mode
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3. N = 2 when Clock Mode 0. N
= 3 when Clock Mode 3.
PHA=1
cs
POL=1
Q4
sclk
Q1
Q3 Q2
Q5
Q15
Q14
Q7
d[0]
d[3:1]
Q6
Q6
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Q14
Q15
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Figure 7-27. QSPI Read (Clock Mode 3)
SPRS85v_TIMING_OSPI1_01
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Timing Requirements and Switching Characteristics 151
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