TDA3MV Datasheet, PDF (221/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
VREF Bypass Capacitor
vdds_ddrx^(A)
VREF Nominal Max Trace
width is 20 mils
0.1 µF
1 K Ω 1%
VREF
DDR2 Controller
0.1 µF
1 K Ω 1%
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
Figure 8-42. VREF Routing and Topology
PCB_DDR2_5
8.8.2.3 DDR2 CK and ADDR_CTRL Routing
Figure 8-43 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
point to point connection with required skew matching.
DDR2 Controller
A’
NO.
RSC21
RSC22
RSC25
RSC26
RSC27
RSC28
RSC29
PCB_DDR2_6
Figure 8-43. CK and ADDR_CTRL Routing and Topology
Table 8-32. CK and ADDR_CTRL Routing Specification
PARAMETER
MIN
Center-to-center ddrx_ck - ddrx_nck spacing
ddrx_ck / ddrx_nck skew
Center-to-center CK to other DDR2 trace spacing⁽²⁾
4w
CK/ADDR_CTRL trace length⁽³⁾
ADDR_CTRL-to-CK skew mismatch
ADDR_CTRL-to-ADDR_CTRL skew mismatch
Center-to-center ADDR_CTRL to other DDR2 trace spacing⁽²⁾
4w
MAX
2w
5
680
25
25
UNIT
ps
ps
ps
ps
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Applications, Implementation, and Layout 221
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