TDA3MV Datasheet, PDF (197/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
• Line spacing:
– For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see Figure 8-18).
W
D+
S = 2 W = 200 µm
SPRS91v_PCB_SE_GND_01
Figure 8-18. Ground Guard Illustration
• Length matching (unless otherwise specified):
– For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
– For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
• Characteristic impedance
– Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
• Multiple peripheral support
– For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
8.4.2 QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
8.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
• The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
• The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
• The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
• The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-19.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 197
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