TDA3MV Datasheet, PDF (212/256 Pages) Texas Instruments – TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
• Maintain a common ground reference for all bypass and decoupling capacitors.
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
8.8.2 DDR2 Board Design and Layout Guidelines
8.8.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-22 and
Figure 8-37.
Table 8-22. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
NO.
DDR21
PARAMETE
R
t_{c(DDR_CLK)}
DESCRIPTION
Cycle time, DDR_CLK
MIN
MAX
UNIT
2.5
8
ns
1
ddrx_ck
PCB_DDR2_0
Figure 8-37. DDR2 Memory Controller Clock Timing
8.8.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
8.8.2.2.1 DDR2 Interface Schematic
Figure 8-38 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-39 the x16
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and
ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not
being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use
of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
212 Applications, Implementation, and Layout
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