XC164-16 Datasheet, PDF(87/417 Page) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Datasheet, PDF (87/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC164-16 Derivatives

Peripheral Units (Vol. 2 of 2)

The Analog/Digital Converter

Field

Bits Type Description

RES

12

rw

Conversion Resolution Control

0 10-bit resolution (default after reset)

1 8-bit resolution

ADCTC

ADSTC

[11:6] rw

[5:0] rw

ADC Conversion Time Control

Defines the ADC basic conversion clock:

fBC = fADC / (<ADCTC> + 1)

ADC Sample Time Control

Defines the ADC sample time:

tS = tBC Ã 4 Ã (<ADSTC> + 1)

Note: The limit values for fBC (see data sheet) must not be exceeded when selecting

ADCTC and fADC.

16.1.2 Enhanced Mode

In enhanced mode (MD = 1), registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN

select the basic functions. The register layout differs from the compatibility-mode layout,

but this mode provides more options.

Conversion timing is selected via registers ADC_CTR2(IN), where ADC_CTR2 controls

standard conversions and ADC_CTR2IN controls injected conversions.

ADC_CTR0

ADC Control Register 0

SFR (FFBEH/DFH)

15 14 13 12 11 10 9 8 7 6 5

MD

SAM

PLE

rw rh

ADCTS

rw

AD AD AD AD AD

CRQ CIN WR BSY ST

rwh rw rw rh rwh

ADM

rw

Reset Value: 1000H

43210

CAL

OFF

rw

ADCH

rw

Field

MD

SAMPLE

Bits Type Description

15

rw

Mode Control

0 Compatibility Mode

1 Enhanced Mode

Note: Any modification of control bit MD is forbidden

while a conversion is currently running. User

software must take care.

14

rh

Sample Phase Status Flag

0 A/D Converter is not in sample phase

1 A/D Converter in sample phase

Userâs Manual

ADC_X41, V2.1

16-5

V2.1, 2004-03

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