XC164-16 Datasheet, PDF (324/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.5 CAN Message Object Buffer (FIFO)
In case of a high CPU load, it may be difficult to process an incoming data frame before
the corresponding message object is overwritten with the next input data stream
provided by the CAN node controller. Depending on the application, it could be also
necessary to ensure a minimum data frame generation rate to fulfill external real time
requirements.
Therefore, a message buffer facility has been implemented in order to avoid a loss of
incoming messages and to minimize the setup time for outgoing messages. Some
message objects can be configured as a base object using succeeding slave message
objects as individual buffer storage (building a circular buffer used as message FIFO).
To / From
CAN Bus
Protocol Layer
Message
Transferred
FIFO Object n + 7
FIFO Object n + 6
FIFO Object n + 5
FIFO Object n + 4
FIFO Object n + 3
FIFO Object n + 2
FIFO Object n + 1
FIFO Object n (base)
Select
Object
Control
Status
FIFO Control Unit
MCA05483
Figure 21-13 FIFO Buffer Control Structure
The number of base and slave message objects, combined to a buffer, has to be a power
of two (2, 4, 8 etc.) and the buffer base address has to be an integer multiple of the buffer
length (e.g. a buffer containing 8 messages can use object 0, 8, 16 or 24 as base object
as illustrated in Table 21-2).
A base object is defined by setting bitfield MMC to ‘010’ in control register MSGFGCRn
and the requested buffer size is determined by selecting an appropriate value for FSIZE.
A slave object is defined by setting bitfield MMC to ‘011’. Bitfield FSIZE has to be equal
in all FIFO elements in the same FIFO.
User’s Manual
TwinCAN_X41, V2.1
21-24
V2.1, 2004-03