XC164-16 Datasheet, PDF (233/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
IrDA Frames
The modulation schemes of IrDA are based on standard asynchronous data
transmission frames. The asynchronous data format in IrDA Mode (M = 010_B) is defined
as follows:
1 start bit/8 data bits/1 stop bit
The coding/decoding of/to the asynchronous data frames is shown in Figure 19-6. In
general, during IrDA transmissions, UART frames are encoded into IR frames and vice
versa. A low level on the IR frame indicates an “LED off” state. A high level on the IR
frame indicates an “LED on” state.
For a 0-bit in the UART frame, a high pulse is generated. For a 1-bit in the UART frame,
no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed
width of 3/16 of the bit time. The ASC also allows the length of the IrDA high pulse to be
programmed. Further, the polarity of the received IrDA pulse can be inverted in IrDA
Mode. Figure 19-6 shows the non-inverted IrDA pulse scheme.
Start
Bit
UART Frame
8 Data Bits
Stop
Bit
0101001101
Start
Bit
IR Frame
8 Data Bits
Stop
Bit
0101001101
Bit Time
1/2-bit Time
Pulse Width =
3/16-bit Time
(or variable length)
MCT05437
Figure 19-6 IrDA Frame Encoding/Decoding
The ASC IrDA pulse mode/width register PMW contains the 8-bit IrDA pulse width value
and the IrDA pulse width mode select bit. This register is required in the IrDA operating
mode only.
User’s Manual
ASC_X, V2.0
19-8
V2.1, 2004-03