XC164-16 Datasheet, PDF (196/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
shadow register can also be done by a write action on MCMOUTS with bit STRHP = 1.
In case of a phase delay (generated by T12 channel 1), a new pattern is applied when
the Multi-Channel mode shadow transfer MCM_ST (indicated by bit STR) occurs.
18.5.2 Sampling of the Hall Pattern
The Hall sensor inputs (CC6POSx) are monitored with the module clock (f_CC6) via an
edge detection block. When a level change is detected on any one of the three inputs, a
signal is generated. In order to suppress spikes on the Hall inputs due to high di/dt in
rugged inverter environment, a hardware noise filter can be used.
This noise filtering is performed using the Dead-Time Counter DTC0. For this function,
the mode control bitfields MSELx for the T12 Channels must all be programmed to
‘1000’. The output signal of the edge detection block is used to trigger DTC0. It is
reloaded, starts counting, and thus generates a delay. An output signal, DTC0_O, is
generated when the counter reaches the value one. This signal is used as the input
sampling and compare evaluation signal HCRDY (see Figure 18-32).
This feature provides a noise filter by delay. Most disturbances, such as switching spikes
and signal bouncing, can be eliminated this way. When an input signal change was
detected, the inputs are sampled a certain time later, determined by the reload value of
DTC0. They are then compared to the current and expected Hall patterns. If the sampled
pattern matches the current pattern (CURH), the detected input signal change was due
to a noise spike (which is not visible anymore), and no further action will be triggered. If
the sampled pattern matches the expected one (EXPH), the signal change was a correct
Hall event, and signal CM_CHE is generated to trigger further actions.
However, when the sampled pattern matches none of CURH and EXPH, the detected
input change lead to a wrong Hall pattern. Signal CM_WHE is generated to indicate this
fault and to allow further appropriate actions.
Figure 18-33 illustrates the noise filter logic.
Edge
Detect
Hall
Compare
Logic
Dead-Time _{DTC0_O}
Gen. Block
DTC0
HCRDY
MCB05537
Figure 18-33 Hall Trigger Logic Block Diagram
User’s Manual
CAPCOM6_X, V2.0
18-52
V2.1, 2004-03