XC164-16 Datasheet, PDF (245/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
19.3.1 Synchronous Transmission
Synchronous transmission begins within four state times after data has been loaded into
TBUF, provided that bit R is set and bit REN is cleared (half-duplex, no reception).
Exception: in Loopback Mode (bit LB set), REN must be set for reception of the
transmitted byte. Data transmission is double-buffered. When the transmitter is idle, the
transmit data loaded into TBUF is immediately moved to the transmit shift register, thus
freeing TBUF for more data. This is indicated by the transmit buffer interrupt request line
TBIR being activated. TBUF may now be loaded with the next data, while transmission
of the previous continuous. The data bits are transmitted synchronous with the shift
clock. After the bit time for the eighth data bit, both the TxD and RxD lines will go high,
the transmit interrupt request line TIR is activated, and serial data transmission stops.
Note: Pin TxD must be configured for alternate data output in order to provide the shift
clock. Pin RxD must also be configured for output during transmission.
19.3.2 Synchronous Reception
Synchronous reception is initiated by setting bit REN. If bit R is set, the data applied at
RxD is clocked into the receive shift register synchronous to the clock that is output at
TxD. After the eighth bit has been shifted in, the contents of the receive shift register are
transferred to the receive data buffer RBUF, the receive interrupt request line RIR is
activated, the receiver enable bit REN is reset, and serial data reception stops.
Note: Pin TxD must be configured for alternate data output in order to provide the shift
clock. Pin RxD must be configured as alternate data input.
Synchronous reception is stopped by clearing bit REN. A currently received byte is
completed, including the generation of the receive interrupt request and an error interrupt
request, if appropriate. Writing to the transmit buffer register while a reception is in
progress has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of a full receive buffer at the time the
reception of the next byte is complete, both the error interrupt request line EIR and the
overrun error status flag OE will be activated/set, provided the overrun check has been
enabled by bit OEN.
19.3.3 Synchronous Timing
Figure 19-13 shows timing diagrams of the ASC Synchronous Mode data reception and
data transmission. In idle state, the shift clock level is high. With the beginning of a
synchronous transmission of a data byte, the data is shifted out at RxD with the falling
edge of the shift clock. If a data byte is received through RxD, data is latched with the
rising edge of the shift clock.
Between two consecutive receive or transmit data bytes, one shift clock cycle (f_BR) delay
is inserted.
User’s Manual
ASC_X, V2.0
19-20
V2.1, 2004-03