XC164-16 Datasheet, PDF (248/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
The output clock of the baudrate timer with the reload register is the sample clock in the
Asynchronous Modes of the ASC. For baudrate calculations, this baudrate clock f_BR is
derived from the sample clock f_DIV by a division by 16.
The ASC fractional divider register ASCx_FDV contains the 9-bit divider value for the
fractional divider (Asynchronous Mode only). It is also used for reference clock
generation of the autobaud detection unit.
f_ASC
R
Fractional
Divider
2
3
FDE
13-bit Reload Register
MUX
f_DIV
13-bit Baudrate Timer
f_BRT
16 ^fBR
Baudrate
Clock
Sample
Clock
BRS
FDE
0
0
1
BRS
0
1
X
Selected Divider
2
3
Fractional Divider
MCA05445
Figure 19-14 ASC Baudrate Generator Circuitry in Asynchronous Modes
Using the Fixed Input Clock Divider
The baudrate for asynchronous operation of serial channel ASC when using the fixed
input clock divider ratios (FDE = 0) and the required reload value for a given baudrate
can be determined by the following formulas:
BG represents the contents of the reload bitfield BR_VALUE, taken as unsigned 13-bit
integer.
The maximum baudrate that can be achieved for the Asynchronous Modes when using
the two fixed clock divider and a module clock of 40 MHz is 1.25 Mbit/s. Table 19-4 lists
various commonly used baudrates together with the required reload values and the
deviation errors compared to the intended baudrate.
Note: FDE must be 0 to achieve the baudrates in Table 19-3. The deviation errors given
in the table are rounded. Using a baudrate crystal will provide correct baudrates
without deviation errors.
User’s Manual
ASC_X, V2.0
19-23
V2.1, 2004-03